Designing digital circuitry requires a clear design of signal timing and the right sequence of signals dependent from each other. Special focus is often on investigating timing behavior, especially, on wave forms of critical signals, like, clock signals. In complex chip designs clock signals run across multiple clock trees and clock meshes to different physical areas of a semiconductor die. In particularly, rising and falling edges of signals require special attention. Displaying this time behavior of these critical signals on and in integrated circuits is paramount for the functionality and reliability of VLSI (very large-scale integrated circuit) chips. Besides the signal waveform in general, the slew rate is a relevant figure of merit and has to be monitored and potentially adapted for meeting design requirements. One of the caveats is that the measurement is required to be made on-chip because of the risk of distortions from the observed signal by external measurement equipment. Therefore, an on-chip signal skew detection is needed.
However, known skew or phase detectors enter a so-called metastable state, i.e., generating zeros and/or ones unpredictably at an output of a flip-flop if the input signals are synchronized. One of the known disadvantages of such a metastable state is that transistor pairs of the flip-flop and following drivers/transistors draw high currents and deteriorate the reliability of the complete system. In order to increase circuit reliability by, e.g., reducing power consumption of large semiconductor chips, it may be desirable to avoid the state of metastability while—at the same time—ensure a high degree of synchronization of distributed clock signals.